Design of Ultra Low power DET Flip-Flop with Power gating technique

1 PG scholar, M.E VLSI Design, Department of ECE, Info Institute of Engineering , Coimbatore. 2 Assistant Professor, Department of ECE, Info Institute of Engineering , Coimbatore. [email protected] _____________________________________________________________________________ _____ Abstract: The advancement of battery operated designs have abundantly increases the memory elements and registers to be operated in ultra low power. That is the this paper we have proposed a design of CT_C DET flip-flop with power gating technique which is the most efficient power consuming reduction technique. The design of the power gating technique involves the pull-up transistor in the Vdd of the circuit and pull-down transistor in the Gnd terminal. This power gating technique reduces the power consumption by more than 40% than that of the existing design.